The present invention relates to a semiconductor memory device, and more particularly to a method of using a 1-transistor type DRAM to store charges associated with binary states.
It is well known that dynamic random access memory (DRAM) devices can be build as integral components on silicon wafers. It is also well known that only the very top surface of these silicon wafers is where the functionally resides for these DRAM semiconductor devices. The remaining thickness of the silicon wafer is often simply used only as a physical support base. The remaining silicon wafer (excepting portions thereof necessary for the device operation) becomes the factor that increases power consumption and decreases driving speed.
It is also well known that Silicon on insulator (SOI) DRAM wafer designs have a functional thickness comparable to those of regular DRAM devices, but require about one-half the area on the chip. These SOI DRAM type devices are also referred to as single transistor ZRAMs (Zero capacitor RAM), capacitorless type DRAMs, single transistor DRAM devices, and also 1-transistor DRAM devices. These types of devices, i.e., 1-transistor DRAM devices promise to nearly double the memory access retrieval speed while using less power. It is thought that partly due to a small junction capacity thereof associated with these 1-transistor DRAM devices high-speed and low-voltage access can be realized due to a low threshold voltage thereof, as compared to a semiconductor device integrated on a general silicon wafer.
FIG. 1 is a cross-sectional view showing a DRAM cell implemented on a conventional SOI wafer. In FIG. 1, an SOI wafer 10 is shown configured as a stacked structure composed of a silicon substrate 1, a buried oxide layer 2 and a silicon layer 3. A device isolating layer 11 defining an activation region on the silicon layer 3 of the SOI wafer 10 is shown formed to adjoin the buried oxide layer 2. A gate 12 is shown formed on an upper surface of the activation region of the silicon layer 3, and the source/drain regions 13a, 13b are shown formed in the silicon layer 3 of the both sides of the gate 12 that adjoin the buried oxide layer 2.
In a DRAM cell implemented on the SOI wafer 10, residual holes and/or electrons are thought to be captured or accumulated within a floating body corresponding to the channel region beneath the gate 12. This charge residual accumulation of either these excess holes or electrons at the channel region beneath the gate 12 can be exploited as a binary scheme to store data or to store information.
For example, as shown in FIG. 2a, storing an arbitrary “1” binary state may be arbitrarily defined as a state where lots of holes are in the floating body. In contrast, as shown in FIG. 2b, storing an arbitrary “0” binary state may be arbitrarily defined as a state where less holes or an excess of electrons are accumulated within this floating body. As a result, during a read state, this excess accumulation of charges are thought to directly contribute to influencing the amount of sensing current flowing across these 1-transistor type cell in either a store “1” state or in the store “0” state.
FIG. 3 graphically depicts a read current as a function of gate voltage when the cell drain voltage Vd is maintained at approximately 0.2V while setting the cell source voltage to ground (GND) for the DRAM cell implemented on the conventional SOI wafer.
As shown, the read current is larger in the store “1” state and is smaller in the store “0” state, wherein reference current is intermediate therebetween.
In the DRAM cell implemented on the aforementioned conventional SOI wafer, there is a need for a method that is capable of effectively writing and reading the data in the low voltage state. A need also exists for a method that is capable of stably driving the 1-transistor type DRAM cell.